ADDAPT has been finished successfully by the end of October 2017.
Many dissemination activities including > 45 scientific publications and two organized workshops, market and competitor analysis verify the uniqueness and that the high impact of the ADDAPT. Therefore, the start-up company CoolOptics was founded for potential exploitation of the ADDAPT technology. In this regard parts of the approaches are IPR protected.
Overall, we could demonstrate record performance on the component and system level. IC design was conducted in a leading edge 14 nm CMOS technology. High-speed VCSEL and photodetectors were designed and corresponding process development was conducted. Electro-optical packaging and assembling techniques for high bandwidths, data rates and low losses were developed. A bandwidth of up to 70 GHz (data rate of 54 Gb/s measured) and insertion loss of less than 2.5 dB was achieved for the complete electrical interface.
The Tx could be electrically measured up to 54 Gb/s (speed limited by the test equipment) and optically up to 45 Gb/s. The receiver could be measured optically, up to 64 Gb/s, the Rx+CDR up to 60 Gb/s and rapid-on functionality of the Rx up to 56 Gb/s. We could demonstrate a rapid-on time of Tx <10 ns, and <7 ns for the Rx at 56 Gb/s, which is beyond the original targets. However, with a data rate of 45 Gb/s (always on) and 40 Gb/s (with rapid-on/off) the measurement of the full optical link fell shy of the 56 Gb/s target. Further refinement of the electrical and optical components would be required to reach this goal. Nevertheless, the overall link performance still extends the current state-of-the-art for optical links in CMOS.The overall link energy efficiency is 4 pJ/bit at 40 Gb/s. With unique adaptive features like rapid on/off switching as well as dynamic bandwidth and power scaling power savings up to 80 % per link were enabled.
Hence, there are several fundamental achievements of the ADDAPT project:
- Demonstration that (low-power) CMOS can be used to build optical components at very high data rates. So far, this was dominated by SiGe implementations.
- By using CMOS the energy consumption can be reduced by a factor of 5-10 compared to a SiGe design.
- Demonstration of rapid-on/off switching (ROOS) with very low latency, enabling per-packet activation of the links.
- Demonstration of “first-bit right” measurements for rapid-on links using packet synchronization
- Demonstration of dynamic performance scaling allowing to reduce the power by a factor of 4 in addition to ROOS.
The technical ADDAPT achievements can be summarized as follows:
- IC technology 14 nm CMOS
- TX IC up to 45 Gb/s (capable of 56 Gb/s electrically) with < 2 pJ/bit
- RX IC up to 64 Gb/s with ~2 pJ/bit
- Design of VCSELs up to 50 Gb/s
- Design of PDs up to 56 Gb/s
- High-speed VCSEL & PD technology
- Packaging technique up to 100 Gb/s
- 1-ch and 4-ch transceiver modules
- Link speed up to 40 Gb/s
- Link efficiency 4 pJ/bit
- 80% power saving by adaptive tuning
- Rapid on/off switching < 10 ns
At the time of finalizing ADDAPT, several world records have been achieved with the results:
- Fastest CMOS optical receiver (64 Gb/s)
- Fastest CMOS optical receiver with CDR (60 Gb/s)
- Lowest power optical receiver above 32 Gb/s
- Fastest CMOS optical transmitter (45 Gb/s)
- Fastest rapid turn-on delay: 7 ns
- CMOS RX showing sensitivity on par with SiGe (around -9 dBm OMA)
- Lowest VCSEL link power consumption above 32 Gb/s (4 pJ/bit)
- Highest HF package bandwidth applied with wire bonding
Detailed results are reported in the Final Report and the 3rd Project Periodic Report. Please have a look at the Deliverable Section. Below two videos of the final verification are posted.
Demonstration of the ADDAPT optical link data transmission
Demonstration of the rapid on/off switching of the ADDAPT link